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6502 project – Designing the Circuit

This is part of my 6502 project, the introduction to which can be found here.

As you can see from the EagleCAD image below (please click it to enlarge) I’ve gotten a basic design down. This includes a WDC 65C02 (the CMOS) version with many of the bugs fixed which were present in the orignal NMOS version.  The circuit also includes a RAM chip, EEPROM (which holds the MOS/firmware/BIOS), a 6522 VIA I/O, and a memory decoder.

(click image to enlarge)

Click here for a black & white version (easier to read).

Also included is a crystal and circuit to create the the 2MHz square wave clock which keeps everything synchronised.  Yep, you read correctly: 2MHz.
I could potentially try and get a 10 or even 100MHz version CPU, but these have their own problems and the slower the clock the easier things are.  I’m not trying to create a replacement PC here, but simply wish to see if I can create my own retro 8 bit computer.

How it works

As you can see from the diagram the centre of the circuit is the 65C02 and as previously stated is the CPU. It has a total of 40 pins, 20 down each side as the one I’m designing for comes in a DIL (dual in-line) package.

I’ve repositioned the pins so that they are grouped together with their relevant neighbours, so data lines are all together as are address lines. Although not physically correct this helps in reading the diagram and is standard practice.

The system has a 16bit address bus (allowing up to 64K (kilobytes) of addressable memory) and an 8bit data bus. These are represented by the blue bus lines in the diagram (address bus is the lower one and the data bus is the higher one).

Clock-wise, the system runs off a 2MHz clock circuit which comprises of a 2MHz crystal, a couple of 1K resistors and an hex inverter IC. This gives not only the clock, but forms it into a square wave output.  This circuit is currently connected to PH0 (pin 37) on the 65C02 and in future diagrams will be connected to the 65C22 as well. I may replace this part of the circuit with an oscillator instead as this seems the recommended way. Unfortunately I can only find 4MHz oscillators and so will have to combine it with a D-type flip-flop to have the frequency.

Initially the computer will run off 32KB of RAM and 8KB of EEPROM (electronically erasable programmable read-only memory). The EEPROM is a Atmel 28C64AP which gives 8KB (64Kb) of non-volatile memory and will contain the BIOS.  RAM-wise, I’ve selected a Cypress Semiconductor CY7C199CN which gives 32KB (256Kb). I have no idea if these will time well with the rest of the circuit so may have to replace them with other devices.
The above to accounts for 48KB of the address space. This leaves 16KB which can be reserved (for now) for input/output operations such as addressing the 65C22.

The IC of choice is the 6522 – or more to the point the CMOS version 65C22 as we really want all devices to be of the same technology if it can be helped. The 65C22 is used to interface devices which cannot be loaded directly on to the address and data buses – such as keyboard, display, serial I/O, etc.. In fact, it's best to keep almost all I/O devices off of the main buses.

[UPDATE - 24th May 2014]

The above was designed when I started this project last year and has since gone through a few changes. These have come about partly because of a greater understanding of what is needed on my part and partly from some excellent advice from the good folks on 6502.org forums.

Here's the new layout (colour to the left, monochrome to the right):

Updated 6502 design in colour Updated 6502 design in black & white
(click an image to enlarge)

As you can see, there's been some significant changes to the layout, circuit and components.

The layout has changed due to the fact that the design was beginning to look like spaghetti junction and so becoming more and more difficult to read. The new design should make things much easier to comprehend (at least I hope so!). The most significant change has been to modularise everything so that the over-all circuit is split into sub-circuits.

The circuit itself has changed along with some components:

The entire clock circuit (74LS04N inverter, 2MHz crystal, etc) has been completely replaced with two possibilities:. A single 2MHz oscillator can which needs no extra components as the primary one to use. The second possibility is a 4MHz oscillator can fed through a D-type flip flop which divides the clock in half to 2MHz. This can be used later if a higher clock speed is needed for either the CPU or to interleave RAM access between CPU and video.

Replaced the CY7C199CN Static RAM chip with a Hyundai 62256B (256kbit, 32 KB) Static RAM chip. As it's predecessor did, this covers addresses &0000 to &3FFF, however only 16K is accessible (&0000 to &3FFF) as the remaining 16K (&4000 to &7FFF) is reserved for I/O. Currently, only &6000-&600F(16 bytes) is utilised which is mapped to a 65C22 VIA.
Replaced the Atmel 28C64AP (64kbit, 8 KB) EEPROM with a Winbound W27C512 (512kbit, 64 KB) EEPROM. Only the top 32KB of the chip is ever used, with everything above &7FFF in the memory map is mapped to the EEPROM. This is because the 65C02 can only ever utilise 64KB at one time and if we left the whole 64KB there we'd have no access to RAM :).

Memory decoding & memory map
The 74LS138 de-multiplexer which decodes the addresses and select the correct IC (RAM, EEPROM, VIA) has been replaced completely with a series of NAND gates which speeds up decoding.

This is the list of the devices which claim space in the memory map:

IC Memory Range Enabling Conditions (address bus bit pattern, x=don't care)
RAM &0000 - &3FFF A15=low, A14=low (00xxxxxx xxxxxxxx)
VIA &6000 - &600F A15=low, A14=high, A13=high (011xxxxx xxxxxxxx)
EEPROM &8000 - &FFFF A15=high, A14=low (10xxxxx xxxxxxxx)

And here's the truth table for the circuit for various read/write operations:

Truth table for 6502 read/write operations
(click image to enlarge)

The NAND gate memory decoding method was provided by Garth Wilson's 6502 primer (it's definitely worth a read). I will at some stage be looking at moving the VIA addresses (&6000-&600F) to the EEPROM address range somewhere as the OS is unlikely to utilise 32KB where-as RAM is always at a premium. Another idea is to fit a much larger RAM module such as a 4mbit (512KB) and then use the VIA in conjunction with a latch to control which part of the address space is paged in to the main memory map. At that stage it might be worth switching to the W65C816S. Food for thought.

There's now a circuit for power which utilises an LM7805 which regulates voltage to 5V for an input voltage of between 7 and 25 volts. It also has a 22uF fast reacting tantalum capacitor for low frequency smoothing on the power rail. Each major IC in the entire design has a 100nF capacitor for dealing with high frequency smoothing.

Reset Switch
My original reset circuit was simply a resistor which held the /RES (RESB) pin on the CPU high until the switch was pressed which pulled it low (the /RES CPU pin is active low).
This solution suffered from switch debounce among other things, an issue where a switch will generate lots of 'pressed' signals during the fraction of a second it takes to press it. This can lead to issues where a an IC gets lots of 'on's and 'off's which can give undesired results. Fortunately, there's a solution to this: Either a reset IC can be utilised or a debounce circuit can be used. Regarding the latter: There are many circuits out there to do this and initially I chose Garth Wilson's one which generates an 80ms pulse - enough to properly reset the older NMOS 6502 CPU without cooking it. However, given that I only plan to use the CMOS version now (which doesn't suffer from overheating if reset for too long), I've switched to the DS1813 reset chip which lessens the component count and is very easy to use.

[UPDATE - 8th Feb 2015]

I've updated the circuit diagram with a few minor changes and also to remove the "Alternative 4MHz from 2MHz clock circuit" as this is not required.

Truth table for 6502 read/write operations
(click image to enlarge)



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