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6502 project – Construction & Testing

[15th February 2015]

This is part of my 6502 project, the introduction to which can be found here.

It's taken me quite a while to write the assembler and plan out the circuit, so I only started constructing this project at the beginning of 2014 and to be honest I haven't rushed this - it's a hobby, not work. The first version started of (as my other projects have) on a solder-less breadboard. For those of you who've not seen one of these, here you go:

breadboard
(click image to enlarge)

Before I go on about the build, here's a list of tools used in building and testing.

 

 

 

Oscilloscope
Bench Power Supply
Multimeter
DS5022S-1200 oscilloscope
CMOSTTLDesigner
HM200digimess multimeter
OWON PDS5022S Dual Channel 25MHz digital oscilloscope
E&L Instruments CMOS/TTL Designer CD-1
digimess HM200 Digital Multimeter
Solder
Solder Station
Wirewrap Tool
Solder
WellerWHS40D solder station
wire-wrap tool
Multicomp 60/40 / Lead free / 0.5mm / Rosin, 250G, O53C990358
Weller WHS 40D Solder station
OK WSU-30M wirewrap tool
EEPROM Programmer
Single Cycle Stepper
BX32II Programmer
Single Cycle Stepper
Batronix Batupo II BX32
See below

Single cycle stepper

The single cycle stepper is a small circuit with a push button on it that can be used in place of a crystal or oscillator. When the button is pressed a single 1Hz (1 microsecond) pulse is generated. Otherwise, the line is held high. this can be used is single step through each cycle of a processor and take measurements off of the various buses and signal lines. Without this, it would be far more difficult to debug.

The circuit design (and credit) belong to Gath Wilson's 6502 Primer.

Here's a couple of pictures of the constructed cycle stepper:

Single Step Cycle Stepper Single Step Cycle Stepper Solder-side
(click an image to enlarge)


Breadboard version

The breadboard version turned out to be a chronic pain to put together and debug due to the amount of wire, lack of resources, and I didn't know as much about digital circuits at the time as I do now (and I don't profess to be an expert - the opposite in fact). I later found out that with regard to high speed digital circuits it can be quite counter productive to use a breadboard due to the amount of extra capacitance generated in the circuit due to the long copper traces in the breadboard itself (as well as in the loops of wire that I'd used). This also exacerbates ringing on the circuit.
This version of the design (as well as the Veroboard version below) utilised a 2MHz oscillator, a de-bounced reset button, a WDC W65C02S CPU, 70ns HY62256B 32KB SRAM, a Winbond W27C512-45Z EEPROM and an 74HC132N NAND gate IC. I didn't bother putting in an IRQ/NMI circuitry and simply pulled such lines high to the +5V rail via a 3K3 resistor.

The circuit did function to a degree, giving correct single step (see below) bus readings when reading from the EEPROM and reading/writing to RAM. My main issues started when I added in the 65C22 VIA. I could in no way get it to output a bit pattern on port A or port B of it's lines. I did an fair amount of testing, checking for short circuits, adequate voltage, correct connection to bus lines, address decoding, and more. His is what really defeated me on this version and ended up restarting the whole thing, but this time on Veroboard.
Here's a picture of the breadboard build hooked up to some LEDs to display the bus binary values:

breadboard_early_6502
(click image to enlarge)

As you can see, it suffers from a heck of a lot of wire loops and looks like a complete rats nest. Also, as advised above, I then discovered that at least some of my issues could be down to simply breading the project in the first place.

Here's a video I took of it being single cycle stepped:


Veroboard version


veroboard_6502_1 veroboard_6502_2
(click an image to enlarge)

Unfortunately, the veroboard version had its own issues and despite an awful lot of diagnostics, I couldn't get it to behave due to corruption on the data bus which I believe was caused by bus contention, although the decoding looked absolutely fine and swapping ICs made no difference. The other issue is that it still has wire loops which, as stated above, leads to extra capacitance. One thing I didn't like about this version was using a veroboard with pre-made tracks as I much prefer single pad perfboards. Here's an example of the copper side of a veroboard to give you an idea of what they look like:

blank veroboard


Wirewrap version

I eventually decided to learn how to build the circuit using wire wrap techniques instead of soldering. Wire wrap is a system where special DIL sockets with inch long legs are utilised. The legs are square rather than round cross-section wise and 30 AWG wire is wrapped around one of the legs using a wire wrap tool (see below) then taken to a destination wire wrap DIL socket and the same is done there. This produces a cold weld and if done well is as good as soldering with the added bonus of keeping all of the wires as short as possible - which minimises stray capacitance and ringing. One very small (in my opinion) down side is that the finish doesn't look as good, but that doesn't both me.

Here's an example of a wirewrap DIL socket and the wirewrapped pins of socket on the underside of a PCB (one of my early attempts):

veroboard_6502_1 veroboard_6502_2
(click image to enlarge)

As this is my latest build and most successful one so far I'm including most of the details. It's built to the latest version of the circuit diagram as of now (version 6a) although I've not included the power regulator circuit (apart form the power LED) as I'm using a bench power source to produce the +5v required. Also, I've not utilised all the 100nF smoothing capacitors specified - one on the CPU, VIA and address decoding IC) is fine.

Here's a parts list:

 

Qty Device Type Primary Task Designation Part Number/Description
1
IC CPU IC1 Western Digital W65C02S6TPG-14 (40 pins)
1
IC BIOS/OS ROM IC8 Winbond W27C512-45Z, 512Kbit (64KB) EEPROM (28 pins)
1
IC Main RAM IC6 HY62256B LLP-70, 256Kbit (32KB) Static RAM (28 pins)
1
IC I/O IC3 Western Digital W65C22S6TPG-14, VIA (40 pins)
1
IC Reset IC10 Maxim DS1813
1
IC Address Decoding IC2 SN74AC132N, Quad NAND, Schmitt trigger (14 pins)
1
IC IRQ Handling IC9 Motorla 74AC11N, AND, Tripple input (14 pins)
1
Oscillator Clock Generator QG2 AEL9700CS, 4MHz (4 pins)
1
Switch Reset button SW1  
4
Resistor Pull up resisitor R6,7,8,9 3K3 resistor
1
Resistor LED current limiter R10 620R resistor
1
LED Display power status D1 5mm Red LED
3
Capacitor Smoothing for ICs C2,4,8 100nF ceramic capacitor
1
PCB PCB (n/a) CIF AFP16 Prototyping PCB 100mm x160mm, Epoxy paper
1
Wire Links (n/a) 30 AWG wirewrap wire
1
DIL socket (n/a) (n/a) 4 pin (14 pin form factor) crystal socket
2
DIL socket (n/a) (n/a) 40 pin Wirewrap DIL socket
2
DIL socket (n/a) (n/a) 28 pin Wirewrap DIL socket
2
DIL socket (n/a) (n/a) 14 pin Wirewrap DIL socket

 

Something to note is the use of single pad perf PCB. The single pads are very useful when dealing with wirewrap designs as we have no use for pre-made tracks as the wirewrap links take their place. A downside is that it makes things a little more difficult when there is a need to solder anything if multiple components/links go to the same point. My prototype has some ugly soldering due to this (that's my excuse, anyway :D></p>
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      [ UNDER CONSTRUCTION ] <br />
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    <p style=). Mostly, this is affects the power rails, although next time I'll be wirewrapping this aspect of the design as well.

Working prototype

Ok, so here we are at last and here is the constructed wirewrap version of my 6502 homerew project. And it works.

wire_wrap_6502_topside wire_wrap_6502_components vwire_wrap_6502_rearside
(click an image to enlarge)

All test instructions, I/O operations (VIA IC included) work as expected. I've also tested it with the following oscillators: 2MHz, 4MHz, 8MHz, 10MHz and 12MHz.
Up to and including 8MHz I had no issues, but ran into instability with 10MHz. As this instability issues seemed to revolve around RAM access, I swapped the HY62256 IC for aToshiba TC55257DPL and it now works fine. Oddly, both are 70ns so I expect that the Toshiba is a little more tolerant of the speed increase. At 12MHz I couldn't get the project to work at all, so for the moment 10MHz is the maximum.

Clock distortion

Whilst running the speed tests I did notice an odd issue when reading the clock speed using my OWON oscilloscope. I found that I was getting the following when measuring the clock at different frequencies:


Oscilloscope 4MHz wave form
Oscilloscope 8MHz wave form
Oscilloscope 10MHz wave form
4MHz
8MHz
10MHz
(click an image to enlarge)

Notice that the wave form becomes humped, giving an odd M / W shape the more the speed is increased. I initially believed this was a symptom of why the circuit wouldn't run at 12MHz, but it turns out that the issue is down to my scope: It cannot properly sample the speed as typically (from what I understand) the scope must be x10 the speed that you're trying to measure to give you a correct/non-distorted measurement. As my scope is rated at 25MHz I'm getting distortion (would be accurate up to 2.5MHz clock). I will at some point be purchasing a 100MHz or greater 'scope, but for the moment will have to live with the distortion and test at lower frequencies if needed and practical.

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